ARL DSRC Doubles its Sustained Performance
In late 2008, the
Army Research Laboratory DoD Supercomputing Resource Center (ARL DSRC) will increase its computing capability
from 100 to 200 TFLOPS. This factor of two increase in capability will make the ARL DSRC one of the most capable
computing centers in the Department of Defense (DoD).
Three Cray XT5s were procured for the ARL DSRC as part of the DoD High Performance Computing Modernization Program’s (HPCMP) Technology Insertion 2008, an initiative to modernize the DoD’s high performance computing capabilities. The HPCMP provides the supercomputer services, high-speed network communications, and computational science expertise that enables the U.S. Defense laboratories, such as the ARL DSRC, to conduct a wide range of focused research, development, and testing activities.
"Today’s scientists are challenged with moving new ideas, technologies and capabilities from concept to warfighter capability more quickly than ever before. This increased computational power will ensure that our scientists and engineers can solve increasingly complex problems in real time, providing our warfighters the latest weapons systems, tactical capabilities and strategic technologies in a reduced timeframe", said Charles J. Nietubicz, Director of the ARL DSRC and Chief of the Advanced Computing and Computational Sciences Division in the Computational and Information Sciences Directorate.
The three Cray XT5s will be installed at the ARL DSRC in the next 7 months. The most powerful of the new systems is a Cray XT5 with 10,400 AMD Opteron processor cores (aka Barcelona). The system will have the largest memory capacity in the HPCMP at 41.6 TB, along with approximately 500 TB of fiber channel attached disk with a bandwidth of 33 GB/s. This system is scheduled for delivery on 15 September 2008 with full acceptance no later than December 11th 2008.
The second Cray XT5 has 1952 processor cores and will support the ARL, Weapons & Material Research Directorate’s recently awarded Dedicated High Performance Computing Project Investment (DHPI) initiative of the HPCMP. DHPI projects requires HPC resources but under time critical constraints (i.e. real-time or near real-time requirement for results), cannot tolerate network latencies, or have other unconventional operating conditions and therefore preclude the use of existing shared resource centers. The DHPI system will arrive in the July timeframe. The ARL DSRC will operate this system on behalf of the WMRD DHPI team, led by Dr. Bob Doney.
The third system is a test and development system with 96 cores, also with 4 GB per core, to be delivered in advance of the other two systems in late June. The Cray and ARL DSRC teams will work closely utilizing this machine for kernel and applications testing. "Ironing the details out on a smaller machine provides our users a positive first experience when they get onto the larger production machines" adds Tom Kendall Deputy Director of Technology and Operations at the DSRC.